1. Field of the Invention
The present invention relates to a magnetic memory cell and a magnetic random access memory. More particularly, the present invention relates a magnetic memory cell in which a tunnel magnetic resistance element and a transistor are combined, and a magnetic random access memory.
2. Description of the Related Art
A magnetic random access memory (MRAM) is known. The magnetic random access memory using magnetic memory cells will be described with reference to U.S. Pat. No. 6,191,989. FIGS. 1A and 1B are diagrams showing the operation principle of a magnetic resistance element contained in a magnetic memory cell. The magnetic resistance element 107 is composed of a free layer 121 having an invertible spontaneous magnetization, a pin layer 123 having a fixed spontaneous magnetization, and a tunnel insulating layer 122 which is interposed between the pin layer 123 and the free layer 121. The free layer 121 is formed in such a manner that the direction of the spontaneous magnetization can oriented to the direction parallel to i.e., the same direction as the direction of the spontaneous magnetization of the pin layer 123, or the direction anti-parallel, i.e., the opposite direction to it.
The resistance of the magnetic resistance element 107 varies based on whether the direction of the spontaneous magnetization of the free layer 121 is parallel to the direction of the spontaneous magnetization of the pin layer 123 or anti-parallel to it. Therefore, a quantity of electric current which flows through the tunnel insulating layer 122 varies. In the magnetic resistance element 107, a data “1” is allocated to one of the “parallel state” and the “anti-parallel state” and a data “0” is allocated to the other. For example, as shown in FIG. 1A, when the directions of the spontaneous magnetizations are anti-parallel, the resistance of the magnetic resistance element 107 is R+ΔR. At this time, if the applied voltage is constant, the quantity of electric current is small. The data “1” is allocated to this state. On the other hand, as shown in FIG. 1B, when the directions of the spontaneous magnetizations are parallel to each other, the resistance of the magnetic resistance element 107 is R and the quantity of current becomes large. The data “0” is allocated to this state.
A semiconductor memory device which uses the magnetic memory cell containing such a magnetic resistance element 107 as memory cell 102 is called a magnetic random access memory. The direction of the magnetization of the pin layer 123 is fixed in the manufacturing. The fixation is often carried out by using anti-ferromagnetic substance layer 134.
FIG. 2 is a cross sectional view showing the memory cell. The memory cell 102 is composed of a magnetic resistance element 107, a MOS transistor 106, a contact wiring line 126, a contact wiring line 127, a contact wiring line 128, and an extension wiring line 129. The MOS transistor 106 has a first diffusion layer 106a, a second diffusion layer 106c and a first gate 106b provided on the semiconductor substrate through an insulating layer between the first diffusion layer 106a and the second diffusion layer 106c. The first diffusion layer 106a is connected with a ground (GND) wiring line 124 through a contact wiring line 128, and the second diffusion layer 106c is connected with one end of the extension wiring line 129 through a contact wiring line 127. The gate 106b is connected with a read word line 104. The extension wiring line 129 is connected at the other end with one end of the magnetic resistance element 107. The magnetic resistance element 107 is connected at the other end with a bit line 105 through a contact wiring line 126. Also, a write word line 103 is provided in the interlayer insulating layer 125 on the side opposite to the bit line 105 with respect to the extension wiring line 129 for the magnetic resistance element 107 to be orthogonal to the bit line 105.
The spontaneous magnetization of the free layer 121 of the magnetic resistance element 107 can be inverted into a desired direction based on a synthetic magnetic field which is generated by the electric current which flows through the bit line 105 and the electric current which flows through the write word line 103.
FIGS. 3A to 3C are diagrams showing the principle of the data write operation into the magnetic memory cell. The vertical axis shows the magnetic field in a Y-axis direction and the horizontal axis is the magnetic field in the X-axis direction, as shown in to FIGS. 1A and 1B and FIG. 2 in correspondence to the memory cell. The magnetic coercivity of the free layer 121 shows a characteristic called an asteroid curve (the magnetization inversion magnetic field curve). When a magnetic field having a strength in the region outside the asteroid curve is applied to the magnetic resistance element, the spontaneous magnetization of the free layer 121 is inverted, because the magnetic field exceeds the magnetic coercivity. The asteroid curve shown in FIGS. 3A to 3C shows that the spontaneous magnetization of the free layer 121 is most easily inverted when the synthetic magnetic field H0 having the angle of 45° with respect to both of the write word line 103 and the bit line 105 which is orthogonal to the write word line 103 is applied to the free layer 121. The electric currents which flow through the bit line 105 and the write word line 103 have been selected in such a manner that the synthetic magnetic field H0 of the magnetic fields which are generated by those electric currents is in the area outside the asteroid curve, and that the magnetic fields HY0 and HX0 which are generated independently by the respective electric currents is present in the area inside the asteroid curve. In this way, through the selection of the electric currents, the data can be written in the magnetic resistance element 107.
FIG. 4 is a diagram showing a conventional magnetic random access memory using the memory cells. The conventional magnetic random access memory is composed of a memory the memory cell array 101, a plurality of write word lines 103, a plurality of read word lines 104, a plurality of bit lines 105, an X-selector 108, an X-side current source circuit 109, an X-side current terminating circuit 110, a Y-selector 111, a Y-side electric current source circuit 112, a read current load circuit 113, a Y-side current terminating circuit 114 and a sense amplifier 115.
In the memory cell array 101, the memory cells 102 are arranged in a matrix. The X-selector 108 selects a desired read word line 104s from the plurality of read word lines 104 extending in the X-axis direction in case of a data read operation, and selects a desired write word line 103s from the plurality of write word lines 103 extending in the X-axis direction in case of a data write operation. The X-side current source circuit 109 has a constant current source, and supplies a constant electric current in the case of the data write operation into the memory cell 102. The X-side current terminating circuit 110 terminates the plurality of write word lines 103. The Y-selector 111 selects desired bit lines 105s from the plurality of bit lines 105 extending in the Y-axis direction. The Y-side electric current source circuit 112 has a constant current source, and supplies a constant electric current in the case of the data write operation into the memory cell 102. The read current load circuit 113 has a constant current source, and supplies a predetermined electric current to the selected memory cell and a reference memory cell 102r in case of the data read operation from the memory cell 102. The Y-side current terminating circuit 114 terminates the plurality of bit lines 105. The sense amplifier 115 detects the data of the selected memory cell 102s based on the difference between a voltage on the reference bit line 105r connected with the reference memory cell 102r and a voltage on the bit line 105 connected with the selected memory cell 102s. 
The memory cell 102 is provided for each of intersections of a plurality of sets of the read word line 104 and the write word line 103 and the plurality of bit lines 105. The memory cell 102 contains a MOS transistor 106 turned on in the selection of the memory cell 102, and the magnetic resistance element 107. The MOS transistor 106 and the magnetic resistance element 107 are connected in series. The magnetic resistance element 107 is shown by a variable resistance symbol because the effective resistance value of the magnetic resistance element 107 varies between R+ΔR and R based on the data of “1” and “0”.
The read operation of the data from the memory cell 102 is carried out as follows. That is, one of the memory cells 102 is selected which is provided for the intersection point of the selected read word line 104s selected by the X-selector 108 and the selected bit line 105s selected by the Y-selector, and the constant electric current is supplied to the magnetic resistance element 107 of the selected memory cell 102s from the read current load circuit 113. Thus, the selected bit line 105s is set to a voltage corresponding to the state of the free layer 121 of the magnetic resistance element 107, i.e., the resistance value of the magnetic resistance element 107. Also, the constant electric current is supplied to the reference memory cell 102r selected based on the bit line 105r and the selected read word line 104s in the same way. Thus, the bit line 105r is set to a predetermined reference voltage. The sense amplifier 115 compares the voltage of the bit line 105r and the voltage of the selected bit line 105 and determines the data of the selected memory cell 102s to be “1” if the voltage of the selected bit line 105s is equal to or larger than the reference voltage and “0” if it is smaller.
The write operation of data into the memory cell 102 is carried out as follows. That is, one of the memory cells 102 is selected which is provided for the point of intersection of the selected write word line 103s selected by the X-selector 108 and the selected bit line 105s selected by the Y-selector, and a magnetic field HY0 and a magnetic field HX0 are generated to the magnetic resistance element 107 of the selected memory cell 102s. Thus, a synthetic magnetic field H0 is generated. Here, the magnetic field HY0 is generated when the electric current flows through the selected write word line 103 from the X-side current source circuit 109. Also, the magnetic field HX0 is generated when the electric current flows through the selected bit line 105 from the Y-side electric current source circuit 112 to have the direction corresponding to the write data. The magnetic resistance element 107 receives the synthetic magnetic field H0 of the magnetic field HX0 and the magnetic field HY0, and the direction of the spontaneous magnetization is inverted in accordance with the write data.
In the magnetic random access memory shown here, data is written in the selected memory cell using the synthetic magnetic field H0 which is formed by the electric current which flows through the selected write word line and the electric current which flows through the selected bit line. The electric current can not be used for the data write operation when the electric current is too small. Also, oppositely, when the electric current is too large, there is a possibility that the data is written in another memory cell connected with the same selected write word line or the same selected bit line, in addition to the selected memory cell. Therefore, the value of electric current which flows through the selected write word line and the value of electric current which flows through the selected bit line are required to have high precise.
The technique which does not have any influence on another memory cell is demanded when the data write operation is carried out to the selected memory cell. The technique which can increase a margin of the electric current for the data write operation is demanded in case of the data write operation. The structure of the memory cell with the high selectivity is demanded when a memory cell is selected from the memory cell array. The technique which can manufacture a nonvolatile memory in a high production yield is demanded. Additionally, the technique which manufactures a nonvolatile memory cheaply is demanded.
In conjunction with the above description, a nonvolatile memory apparatus is disclosed in Japanese Laid Open Patent Application (JP-P2002-230965A). The nonvolatile memory apparatus of this conventional example contains in a memory cell having a magnetic resistance element whose resistance value changes depending on the direction of the magnetization, and 1-bit data is stored in the memory cell. Here, the memory cell has a plurality of sub-cells, each of which contains at least one magnetic resistance element. The sub-cells are connected in series or parallel. The sub cell is composed of the plurality of magnetic resistance elements connected in series or parallel and one selection transistor. Also, the memory cell may be composed of the plurality of sub cells connected in series or parallel. This technique has purposes of improving the record reliability of the magnetic random access memory, realizing the read of data with high reliability even if a deviation between resistance values is present with some degree, and eliminating bias voltage dependence on the MR ratio of the magnetic resistance element.
Also, a ferromagnetic memory and a data reading method are disclosed in Japanese Laid Open Patent Application (JP-P2002-140889A). The ferromagnetic material memory of this conventional example has a variable resistor, a magnetic field generating section, a holding circuit and a signal detecting circuit. The variable resistor consists of a magnetic substance and has a soft layer where data is stored based on the direction of magnetization, a non-magnetic layer, and a soft layer which consists of magnetic substance with magnetic coercivity smaller than a hard layer. The magnetic field generating section initializes the magnetization of the soft layer and also inverts it from the initialization state. The holding circuit holds a resistance value in the initialization state. The signal detecting circuit compares the resistance value of the variable resistor after inversion and the resistance value held in the holding circuit and outputs a reproduction signal. This technique has the purposes of decreasing a cell area and detecting stored data stably in the 1T1R type magnetic random access memory.
Also, a magnetic random access memory is disclosed in Japanese Laid Open Patent Application (JP-P2002-100181A). The magnetic random access memory of this conventional example is composed of a plurality of sense lines, a plurality of word lines provided to extending in a direction orthogonal to the plurality of sense lines, and unit memory cells, which are arranged like an array, and each of which is provided in each of intersections of the sense lines and the word lines. In the unit memory cell, a cell selection switch and a magnetic resistance element are connected in series. The magnetic random access memory of this conventional example further has a condenser which is connected with a power supply through a switch and a voltage drop element which connects one end of the condenser and the sense line. One end of the condenser is used as a detection end of the voltage change corresponding to the data stored in the unit memory cell. This technique has the purposes of widening an operation margin while characteristic deviation between the magnetic resistance elements is excluded, of preventing the decrease of the detection sensitivity of the read circuit (sense amplifier) due to the voltage drop by the wiring line connected with the magnetic resistance element in series and by the resistance of the transistor brings, and preventing the bias effect of the magnetic resistance element and the destruction of the tunnel barrier.